1. Field of the Invention
The present invention relates to a semiconductor device such as a bipolar transistor, or a semiconductor device of a BiCMOS type or the like, including a bipolar transistor and a MOS transistor, and a method of manufacturing such a device, particularly, an element isolation technique.
2. Description of the Related Art
According to a conventional element isolation technique used for a semiconductor device, after forming a field oxide film by a LOCOS method, a deep trench is formed in a silicon substrate, and the surface of the silicon substrate is subjected to a thermal oxidation, in order to fill the inside of the trench will polysilicon, as can be seen in FIGS. 1A to 1E. Such an element isolation structure is disclosed in, for example, Hiroshi Goto et al. "A New Isolation Technology For Bipolar VLSI LOGIC (IOP-L)", Symposium on VLSI Technology, 1985. According to a conventional element isolation technique used for a semiconductor device, after forming a deep trench is formed, the inside of the trench and the surface of the substrate are oxidized at the same time by a LOCOS method, and the inside of the trench is filled with polysilicon, as can be seen in FIGS. 2A to 2D. Such an element isolation structure is disclosed in, for example, U.S. Pat. No. 5,332,683.
More specifically, according to the former technique, first, as shown in FIG. 1A, the main surface of a silicon substrate 11 is subjected to a thermal oxidation, so as to form an SiO.sub.2 film 12, and then a Si.sub.3 N.sub.4 film 13 serving as an anti-oxidization film is formed on the SiO.sub.2 film 12. Then, the Si.sub.3 N.sub.4 film 13 is etched so that the patterned film remains on the element region. Next, as shown in FIG. 1B, the main surface of the substrate 11 is subjected to a thermal oxidation using the Si.sub.3 N.sub.4 film 13, and thus a field oxide film 14 is formed. After that, the Si.sub.3 N.sub.4 film 13 is removed, and a Si.sub.3 N.sub.4 film 15 is formed on the SiO.sub.2 film 12 and the field oxide film 14. Then, a CVD-SiO.sub.2 film 16 is formed on the Si.sub.3 N.sub.4 film 15 to prepare what is shown in FIG. 1C.
Subsequently, trenches 17-1 and 17-2 both having a sufficient depth are formed in the substrate 11 by anisotropic etching such as of an RIE method (see FIG. 1D). The surface portion of the substrate 11, which is exposed inside the trenches 17-1 and 17-2 is subjected to thermal oxidation, so as to form oxide films 18-1 and 18-2. Then, the trenches 17-1 and 17-2 are filled with polysilicon layers 19-1 and 19-2, and the surface portions of the polysilicon layers 19-1 and 19-2 in the trenches 17-1 and 17-2 are thermal-oxidized, thus forming SiO.sub.2 films 20-1 and 20-2. After that, the CVD-SiO.sub.2 film 16 and the Si.sub.3 N.sub.4 film 15 are removed to obtained an element isolation structure as shown in FIG. 1E.
Subsequently, though not shown in the figures, a semiconductor element such as a bipolar transistor or the like, is formed by a conventional manufacturing method, within an element region which is isolated by the field oxide film 14 and the trenches 17-1 and 17-2.
In the meantime, according to the latter method, as can be seen in FIG. 2A, the main surface of the silicon substrate 21 is thermal-oxidized to form an SiO.sub.2 film 22, and a Si.sub.3 N.sub.4 film which serves as an oxidation-resisting film, is formed on the SiO.sub.2 film 22. After that, the Si.sub.3 N.sub.4 film 23 is etched so that the patterned film remains on the element region. Then, a CVD-SiO.sub.2 film 24 is formed on the entire surface of each of the SiO.sub.2 and the Si.sub.3 N.sub.4 film. Next, the CVD-SiO.sub.2 film 24, the SiO.sub.2 film 22 and the substrate 21 in the region in which a field oxide film is to be formed, is selectively etched by anisotropic etching such as an RIE method, so as to prepare trenches 25-1 and 25-2 each having a sufficient depth. Subsequently, the portions of the SiO.sub.2, which are not masked by the CVD-SiO.sub.2 and the Si.sub.3 N.sub.4 film 23, are removed, and the surface of the substrate 21 is exposed as can be seen in FIG. 2C. Subsequently, with use of the Si.sub.3 N.sub.4 film 23 as a mask, the surface of the substrate 21 and the surface of the portion of the substrate 21 which are exposed within the trenches 25-1 and 25-2 are selectively oxidized, and thus a SiO.sub.2 film 26 serving as a field oxide film is formed as shown in FIG. 2D. After that, the trenches 25-1 and 25-2 are filled with the polysilicon layers 27-1 and 27-2, and the exposed surfaces of the polysilicon layers 27-1 and 27-2 are thermal-oxidized so as to form the SiO.sub.2 films 28-1 and 28-2. Then, after removing the portion of the Si.sub.3 N.sub.4 film 23, which remains on the element region, a semiconductor element such as a bipolar transistor, is formed within the element region by a conventional manufacturing method.
However, with the conventional method of forming an element isolation region, in which a field oxide film is formed by the LOCOS method as described above, a bird's beak having a width equivalent to the thickness of the field oxide film is inevitably formed. Therefore, the element region must be enlarged by an area corresponding to the bird's beak, making it difficult to increase the degree of integration. Further, when the bird's beak is large, the parasitic capacitance in that area becomes large, making it difficult to increase the speed of processing in the device.
Moreover, with the method of filling the inside of a trench for isolating an element with a polysilicon layer, it is necessary to form an insulation film such as a thermal oxidation film, on the side wall of the trench for isolation of the element. As a result, a parasitic capacitance is formed between the polysilicon layer buried in a trench, and a silicon substrate, making it difficult to increase the processing speed of the element.
As described above, with the conventional semiconductor device and the method of manufacturing such a device, the element isolation region serves to make it difficult to increase the degree of integration, and a parasitic capacitance is formed in the element isolation region, making it difficult to increase the switching speed of the device.